The present invention relates to a method for fabricating a semiconductor memory device; and more particularly, to a method for fabricating a capacitor of a semiconductor memory device.
A DRAM (Dynamic Random Access Memory) cell is a semiconductor memory device typically comprising one transistor and one capacitor, in which one bit of data is stored in a cell by using an electric charge. A capacitor comprises of a lower electrode, a dielectric layer, and an upper electrode. One electrode of the capacitor is connected to the source/drain junction of the transistor. Another electrode of the capacitor is connected to a reference voltage line.
Advances in computer applications have increased the demand for higher capacity memory chips. Decreasing the size of the memory cells allows more memory cells to be packed into an integrated circuit.
The capacitance of a capacitor is proportional to the surface area of the electrodes and a dielectric constant of a dielectric layer. As the area of the memory cell has decreased, the capacitance of the capacitors tends to decrease also, lowering the performance of the memory cells.
In order to increase the density of memory cells, stacked capacitors have been proposed. Stacked capacitors are formed by partially stacking the storage electrode over the transistor and over the bit/word line, thereby effectively reducing the area used for each memory cell.
A plug is used to connect the lower electrode of the capacitor with the source/drain junction of the transistor.
A method for fabricating a capacitor of a semiconductor memory device according to a first conventional method is described referring to FIG. 1A to FIG. 1C.
As shown in FIG. 1A, an insulating layer 15 is formed over a semiconductor substrate 10, an isolation layer 11, such as field oxide layer, and a transistor comprising a gate insulating layer 12, a gate electrode 13 and source/drain junctions 14. Thereafter, a plug 16 is formed in the insulating layer 15. The plug 16 is composed of a ploysilicon layer 16A, an ohmic contact layer 16B and a diffusion barrier layer 16C formed in a contact hole, exposing one of the source/drain junctions 14.
As shown in FIG. 1B, a lower electrode 17 is formed on the diffusion barrier layer 16C by depositing and patterning a first conductive layer. The diffusion barrier layer 16C may be exposed during the formation of the lower electrode 17 because of a mask misalignment. The mask misalignment is frequently occurred in a manufacturing process of a highly integrated device.
As shown in FIG. 1C, a dielectric layer 18 is formed on the lower electrode 17 and an upper electrode 19 is formed on the dielectric layer 18. The dielectric layer 18 is formed with a material exhibiting a very high dielectric constant, such as Barium strontium titanate (BaSrTiO3, hereafter abbreviated BST), to increase the capacitance in a highly integrated device.
An electro plating technique is used to form the lower electrode without etching process.
A method for fabricating a capacitor of a semiconductor memory device according to a second conventional method, by using the electro plating technique, is described referring to FIG. 2A to FIG. 2E.
As shown in FIG. 2A, an insulating layer 15 is formed over a semiconductor substrate 10, an isolation layer 11, such as field oxide layer, and a transistor comprising a gate insulating layer 12, a gate electrode 13 and source/drain junctions 14. Thereafter, a plug 16 is formed in the insulating layer. The plug 16 is composed of a ploysilicon layer 16A, an ohmic contact layer 16B and a diffusion barrier layer 16C formed in a contact hole, exposing one of the source/drain junctions 14.
As shown in FIG. 2B, a seed layer 21 is formed on the insulating layer 15 and the plug 16, thereafter a glue layer 22 and a sacrificial layer 23 are stacked, one by one, on the seed layer 21.
As shown in FIG. 2C, the sacrificial layer 23 and the glue layer 22 is selectively etched to form opening exposing the seed layer 21, and a lower electrode 17 is formed on the seed layer 21 in the opening.
As shown FIG. 2D, the sacrificial layer 23, the glue layer 22 and the seed layer 21 are removed to separate neighboring the lower electrodes 17.
As shown in FIG. 2E, a dielectric layer 18 is deposited on the lower electrode 17 and the insulating layer 15. Thereafter, an upper electrode 19 is formed on the dielectric layer 18.
In the preceding process of the second conventional method, the diffusion barrier layer 16C of the plug 16 may be exposed after removing the seed layer when the mask misalignment is occurred in the process for forming the opening.
According to the above described conventional methods, the exposed part of the diffusion barrier layer 16C of the plug 16 is contacted to the dielectric layer 18.
There are several problems generated by the contact between the diffusion layer 16C and the dielectric layer 18. One problem is that the diffusion barrier layer 16C is oxidized during the process for forming the dielectric layer 18, because the dielectric layer 18, such as the BST layer, is formed under oxygen gas atmosphere and at a high temperature. The oxidized part of the diffusion barrier layer 16C, exhibiting low dielectric constant, plays a role of a dielectric layer of a capacitor, thereby the capacitance of the capacitor is reduced. The other problem is that the work function difference, between the diffusion barrier 16C and the dielectric layer 18, is low, thereby the leakage current is increased because of the low Schottky barrier height.
It is, therefore, an object of the present invention to provide a semiconductor memory device and a fabrication method capable of preventing the contact between a dielectric layer of a capacitor and a diffusion barrier of a plug.
It is, therefore, another object of the present invention to provide a semiconductor memory device and a fabrication method capable of preventing the lowering the capacitance of a capacitor and the increasing the leakage current between the lower electrode of a capacitor and a diffusion barrier of a plug.
In accordance with an aspect of the present invention, there is provided a semiconductor memory device, comprising: a semiconductor substrate, wherein a gate electrode is formed on the semiconductor substrate, and wherein source/drain junctions are formed in the semiconductor substrate; an interlayer insulating layer formed over the semiconductor substrate; a plug formed in the interlayer insulating layer, wherein the plug comprises a diffusion barrier layer and a seed layer for a electro plating; a lower electrode of capacitor contacted to the seed layer; a dielectric layer formed on the lower electrode; and an upper electrode formed on the dielectric layer.
In accordance with another aspect of the present invention, there is provided a method for fabricating semiconductor memory device, comprising the steps of: providing a semiconductor substrate, wherein a gate electrode is formed on the semiconductor substrate, and wherein source/drain junctions are formed in the semiconductor substrate; forming an interlayer insulating layer over the semiconductor substrate; etching the interlayer insulating layer to form a contact hole; forming a plug in the contact hole, wherein the plug comprises a diffusion barrier layer and a seed layer for a electro plating; forming a lower electrode of a capacitor contacted to the seed layer by using an electro plating technique; forming a dielectric layer of the capacitor on the lower electrode; and forming an upper electrode of the capacitor on the dielectric layer.
In accordance with still further another aspect of the present invention, there is a method for fabricating semiconductor memory device, comprising the steps of: providing a semiconductor substrate, wherein a gate electrode is formed on the semiconductor substrate, and wherein source/drain junctions are formed in the semiconductor substrate; forming an interlayer insulating layer over the semiconductor substrate; etching the interlayer insulating layer to form a contact hole; forming a plug in the contact hole, wherein the plug comprises a diffusion barrier layer and a seed layer for a electro plating; forming a glue layer on the seed layer and the interlayer insulating layer; forming a sacrificial layer on glue layer; etching the sacrificial layer and the glue layer to form an opening defining a region of a lower electrode of a capacitor; forming the lower electrode on the seed layer in the opening, by using an electro plating technique; removing the sacrificial layer and the glue layer; forming a dielectric layer of the capacitor on the lower electrode; and forming an upper electrode of the capacitor on the dielectric layer.